Title :
A Radix-10 Combinational Multiplier
Author :
Lang, Tomás ; Nannarelli, Alberto
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA
fDate :
Oct. 29 2006-Nov. 1 2006
Abstract :
In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.
Keywords :
combinational circuits; counting circuits; multiplying circuits; pipeline arithmetic; adder; counter; operand recoding; partial product precomputation; pipeline arithmetic; radix-10 combinational decimal multiplier; Arithmetic; Computer science; Counting circuits; Delay; Hardware; Informatics; Throughput;
Conference_Titel :
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0784-2
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2006.354758