Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material

In recent years tunnel FETs (TFETs) have attracted a great deal of attention. The reason for this is that TFETs potentially allow beating the 60 mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an on-state performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60 mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.