Design and FPGA Implementation of the Fast Algorithm for Extracting Laser Line

A fast algorithm of extracting laser line is proposed for real-time image processing in 3DLCS and is compared with the former algorithm. First of all, the threshold S(T) of the laser stripe is computed by host computer unnecessarily in real time. Second the laser stripe is determined in real time. At last the central line of the laser stripe is detected by templates in real time. The fast algorithm was successfully implemented using VC6.0, then simulated successfully programming with Verilog HDL on the ¿Verilog XL¿ software which is developed by CANDENCE corporation. The fast algorithm is implemented by FPGA designed as pipelined architecture. The average time of processing every pixel in each step is less than 74ns. The results of emulation and synthesis show that extracting laser line from a frame of standard PAL video image is completed within 40ms. The advantages of the fast algorithm include easy computing, less data throughput, and fast implementation, etc. It reduces greatly information redundancy.