DocumentCode :
2454995
Title :
Profile-based dynamic voltage scheduling using program checkpoints
Author :
Azevedo, Ana ; Issenin, Ilya ; Cornea, Radu ; Gupta, Rajesh ; Dutt, Nikil ; Veidenbaum, Alex ; Nicolau, Alex
Author_Institution :
Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
fYear :
2002
fDate :
2002
Firstpage :
168
Lastpage :
175
Abstract :
Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task scheduling algorithms to implement DVS under operating system control, new research challenges exist in intra-task DVS techniques under software and compiler control. In this paper we introduce a novel intra-task DVS technique under compiler control using program checkpoints. Checkpoints are generated at compile time and indicate places in the code where the processor speed and voltage should be re-calculated. Checkpoints also carry user-defined time constraints. Our technique handles multiple intra-task performance deadlines and modulates power consumption according to a run-time power budget. We experimented with two heuristics for adjusting the clock frequency and voltage. For the particular benchmark studied, one heuristic yielded 63% more energy savings than the other. With the best of the heuristics we designed, our technique resulted in 82% energy savings over the execution of the program without employing DVS
Keywords :
CMOS digital integrated circuits; integrated circuit design; logic simulation; low-power electronics; microprocessor chips; processor scheduling; program compilers; CMOS circuit delay; CPU energy consumption; compiler control; intra-task DVS technique; multiple intra-task performance deadlines; power consumption; processor speed; processor voltage; profile-based dynamic voltage scheduling; program checkpoints; run-time power budget; Control systems; Degradation; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Operating systems; Program processors; Scheduling algorithm; Time factors; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998266
Filename :
998266
Link To Document :
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