DocumentCode :
2455100
Title :
New Efficient Check Node Update Method for Improved Min-Sum LDPC Decoding
Author :
Xin, Lu ; Jun, XU ; Yong-sheng, Liang
Author_Institution :
Shenzhen Inf. Technol. Inst., Shenzhen
fYear :
2007
fDate :
23-27 Sept. 2007
Firstpage :
152
Lastpage :
156
Abstract :
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of normalized min-sum algorithm, if the current row weight is dc, dc multiplications are needed. If dc is large, dc multiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of multiplication operations for the normalized min-sum algorithm and the number of comparison/selection operations for the row weight matched min-sum algorithm of high rate LDPC codes. Simulations have claimed the performance of normalized min-sum and row weight matched min-sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that normalized min-sum and row weight matched min-sum are good choices for LDPC.
Keywords :
decoding; parity check codes; check node update method; hardware architecture; low density parity check codes; min-sum LDPC decoding; normalized min-sum algorithm; row weight matched min-sum algorithm; AWGN; Analytical models; Delay effects; Gaussian channels; Hardware; Information technology; Iterative decoding; Parity check codes; Performance analysis; Turbo codes; BP; CNU; LDPC; Min-Sum;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Design and Its Applications in Communications, 2007. IWSDA 2007. 3rd International Workshop on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-1074-3
Electronic_ISBN :
978-1-4244-1074-3
Type :
conf
DOI :
10.1109/IWSDA.2007.4408346
Filename :
4408346
Link To Document :
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