Title :
Impacts of NBTI on SRAM array with power gating structure
Author :
Yang, Hao-I ; Chuang, Ching-Te ; Hwang, Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected cells also impacted SRAM RSNM and WM. The leakage currents and virtual supply bounce were reduced, but wake-up time became longer. Longer precharge phase and judicious choice of sense amplifier structure would improve the tolerance to NBTI effects.
Keywords :
CMOS memory circuits; SRAM chips; stress analysis; CMOS technology; NBTI; PMOS-type precharge circuits; SRAM array; power gating structure; read-SNM; size 32 nm; threshold voltage; write-margin; CMOS technology; Degradation; Frequency; Logic; Niobium compounds; Predictive models; Random access memory; Stress; Titanium compounds; Writing;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2009.5159298
