FPGAs in digital testing

This paper describes the techniques used to design an interface device (ID) for digital testing, based on field programmable gate arrays (FPGAs). The application reviewed comes from a CASS TPS development program, where 31 digital shop replaceable assemblies (SRAs) were grouped in a single ID. The ID consists of a set of FPGAs interconnected in an optimum mode to match each particular UUT interface requirements. FPGAs are basically used to alter the mapping of resources between UUTs and the ATE. The main advantage of the proposed solution is that the interface hardware can be modified by SW, and what is more, can be also altered during test program execution. The main objective is to provide the reader with a practical methodology for using FPGAs in future TPS developments. Since the circuits implemented on the FPGAs are also needed for the ATPG model, the information of the specific interface is extracted from the LASAR (ATPG environment) files and post-processed to obtain a VHDL (hardware description language) model. The details on how this is performed, with examples, are reviewed in depth.