• DocumentCode
    2455240
  • Title

    CMOS technology roadmap projection including parasitic effects

  • Author

    Wei, Lan ; Boeuf, Frédéric ; Skotnicki, Thomas ; Wong, H. S Philip

  • Author_Institution
    Stanford Univ., Stanford, CA, USA
  • fYear
    2009
  • fDate
    27-29 April 2009
  • Firstpage
    78
  • Lastpage
    79
  • Abstract
    In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32 nm technology. Capacitance components are analytically modeled and different design rules are examined.
  • Keywords
    CMOS integrated circuits; integrated circuit modelling; CMOS technology roadmap projection; Si; parasitic capacitance modelling; parasitic effects; Boosting; CMOS technology; Delay estimation; Integrated circuit interconnections; Inverters; Logic devices; MOS devices; Parasitic capacitance; Semiconductor device modeling; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    978-1-4244-2784-0
  • Electronic_ISBN
    1524-766X
  • Type

    conf

  • DOI
    10.1109/VTSA.2009.5159299
  • Filename
    5159299
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2455240