Title :
Generalized early evaluation in self-timed circuits
Author :
Thornton, M.A. ; Fazel, K. ; Reese, R.B. ; Traver, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Mississippi State Univ., MS, USA
Abstract :
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases
Keywords :
asynchronous circuits; delay estimation; logic design; asynchronous circuits; circuit delay reduction; delay insensitivity; early evaluation functions; generalized early evaluation; local transformations; phased logic; self-timed circuitry; synthesis optimization; Circuit synthesis; Clocks; Cost accounting; Delay; Feedback loop; Field programmable gate arrays; Logic circuits; Logic design; Output feedback; Throughput;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998281
