The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

Author

Parvais, B. ; Mercha, A. ; Collaert, N. ; Rooyackers, R. ; Ferain, I. ; Jurczak, M. ; Subramanian, V. ; De Keersgieter, A. ; Chiarella, T. ; Kerner, C. ; Witters, L. ; Biesemans, S. ; Hoffman, T.

Author_Institution

IMEC, Leuven, Belgium

fYear

2009

fDate

27-29 April 2009

Firstpage

80

Lastpage

81

Abstract

Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached at the same time. V_T mismatch smaller than 3 mV.mum is obtained for narrow (10 nm) fins. Reduced speed sensitivity to gate pitch scaling and invertor delay reduced below 10 ps will be demonstrated.

Keywords

CMOS integrated circuits; MOSFET; mixed analogue-digital integrated circuits; CMOS technology; FinFET technology; gate pitch scaling; invertor delay; mixed-signal domain; planar MOSFET; short channel effect; transconductance; voltage gain; CMOS technology; Delay; FinFETs; High K dielectric materials; High-K gate dielectrics; Immune system; MOS devices; MOSFET circuits; Parasitic capacitance; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-2784-0

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2009.5159300

Filename

5159300