Sub-32nm CMOS technology enhancement for low power applications

Author

Huang, R.M. ; Liu, P.W. ; Liu, E.C. ; Chiang, W.T. ; Tsai, S.H. ; Tsai, Jonas ; Shen, Tzermin ; Tsai, C.H. ; Tsai, C.T. ; Ma, G.H.

Author_Institution

United Microelectron. Corp. (UMC), Tainan, Taiwan

fYear

2009

fDate

27-29 April 2009

Firstpage

86

Lastpage

87

Abstract

In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In addition, the optimized integration scheme can reduce NMOS extension resistance. The main cause is that post e-SiGe clean processes would loss the extension dopant and increases the extension resistance. We successfully reduce the NMOS total resistance 22% compared to control without compromise PMOS device performance.

Keywords

CMOS integrated circuits; Ge-Si alloys; CMOS technology; NMOS extension resistance; PMOS device performance; SiGe; device drive current; performance enhancement; silicide resistance reduction; CMOS technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-2784-0

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2009.5159303

Filename

5159303