A segmentation-based BISR scheme

With memory estate increasing in System-On-Chips and highly integrated products, memory defects and wearout effects are the determining factor in the chip´s yield loss and reliability. In this paper, a multiple cache-based Built-in Self-Repair scheme is proposed that is able to repair from the word level down to the bit level. Moreover, it is proved that the level of segmentation does not affect the repair efficiency. An exploration is then conducted to find the optimal scheme in terms of area overhead.