• DocumentCode
    2455646
  • Title

    Gate level fault diagnosis in scan-based BIST

  • Author

    Bayraktaroglu, Ismet ; Orailoglu, Alex

  • Author_Institution
    Comput. Sci. & Eng. Dept., California Univ., La Jolla, CA, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    376
  • Lastpage
    381
  • Abstract
    A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through numerous experimental runs on all three fault models
  • Keywords
    automatic testing; boundary scan testing; built-in self test; fault diagnosis; fault location; integrated circuit testing; logic testing; automated fault diagnosis scheme; bridging faults; failing test vector information; fault capturing scan chain information; fault models; gate level fault diagnosis scheme; location identification; multiple stuck-at faults; pass/fail dictionaries; scan-based BIST designs; single stuck-at faults; Automatic testing; Built-in self-test; Clocks; Computer science; Design engineering; Dictionaries; Fault diagnosis; Memory; Performance evaluation; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998301
  • Filename
    998301