Fermi level depinning for the design of III–V FET source/drain contacts

High mobility III-V compounds is a strong contender for extending high performance logic beyond the 22 nm technology node. However, demonstrations of exceptional III-V performance required device footprints on the mum-scale despite nm-scale gate lengths, in order to avoid source/drain shorting during contact alloying. The scaling of III-V FETs is severely limited by the unacceptably large lateral diffusion of the multilayer alloyed structures typically used for ohmic contacts. In our recent work, we introduced a novel non-alloyed, highly scalable contact structure through the use of Al as a low workfunction metal on an unpinned Fermi level. We use GaAs as a baseline III-V material, where the developed contact techniques can be extended to InGaAs and InSb, materials which are more technologically important. In this work, we explain in detail the unpinning mechanisms and the rationale for the material selection. We demonstrate the same method can be applied to a variety of metals, Y, Er, Al, Ti, W, and Pt, providing much flexibility in the design of an ideal source/drain contact for III-V HEMTs/MOSFETs and Schottky Barrier FETs.