The influence of thermoelectric effects on the self-heating of nanometer CMOS-SOI devices

In this study we use the measured threshold voltage as the “thermometer” to determine the true channel temperature. The self-heating effects are measured using a careful calibration of the process temperature dependent parameters such as the threshold voltage, mobility and non-ideality factor. It is shown that the temperature rise is significant, approximately 100K above room temperature, even for transistors with relatively low applied power (~ 0.1 mWatt). The CMOS-SOI transistors were designed and fabricated using a standard partially depleted 180 nm CMOS-SOI process. The induced self-heating may result in higher device temperature than predicted by the conventional steady-state thermal analysis. Modeling based on channel´s thermoelectric effects is applied to account for the observed local-heating. The results of this study have an impact on circuit design and may be extended to regular submicron CMOS technology.