A comparison study of Silicon Nanowire Transistor with Schottky-Barrier source/drain and doped source/drain

Schottky barrier (SB) S/D nanowire transistor (SB-NWT) is considered to be one of the candidates for future CMOS technology due to the combination of the advantages both from silicon nanowire (NW) transistor (SNWT) and metal S/D. However, previous studies, both simulations and experiments, show that the electrostatic properties (EPs) of SB-NWTs are not promising. In this paper, SB-NWTs is comprehensively studied in comparison with SNWTs. The SB impact is found to be responsible for the degraded EPs and contributes to unexpectedly large linear region resistance (R_lin). Several approaches to minimize the SB impact are studied and limitations of the approaches are investigated in comparison with SNWTs. Whether SB-NWTs can show better performance than SNWTs will be further discussed.