VLSI design and realisation of a 4 input high speed fuzzy processor

This paper describes the architecture of a VLSI fuzzy chip designed to run at very high speed: the processing rate is 320 ns when 4 inputs are processed, whichever is the fuzzy system. This processing rate is higher if less than 4 inputs are processed and reaches 100 ns for two inputs. The chip has been designed in 0.7 μm CMOS technology, its architecture is pipeline and only the actives rules are processed. To do that the fuzzy system to be processed is first converted in an equivalent one where all the rules are present and then it is loaded in the chip memory. Because of the dimension of the chip rule memory it is possible to construct such a chip when the 4 inputs have no more than 7 Membership Functions, MFs, for each input and the overlapping of the input MFs is not higher than two. The design has been done in VHDL language and it has been synthesized by the Cadence Opus SW obtained via Europractice. This chip has been sent to the ES2 foundry last december to be constructed, we received it back at the end of February and recently it has been successfully rested. At the end of the paper the chip layout is described