Data retention voltage detection for minimizing the standby power of SRAM arrays

Lowering the supply voltage can substantially decrease SRAM leakage power. There are several different approaches to determine the minimum standby voltage at which an SRAM array can preserve its data, also known as the array´s Data Retention Voltage (DRV). The main goal of these approaches is to try and find the tail of the DRV distribution, since the worst SRAM bit cell sets the DRV of an entire memory block. The analytical approach concentrates on solving the sub-threshold voltage-transfer-characteristic equations of the core of a standard 6T bit cell. Another straight-forward method is running numerous Monte Carlo simulations to obtain the DRV at the required probability level. More advanced approaches based on static noise margin statistics remain valid for the extreme tails of the DRV distribution. Finally, the most accurate method is to use designated on-chip hardware to measure the DRV post-silicon fabrication. This paper overviews several recently proposed methods for DRV estimation and determination and discusses the advantages and trade-offs of these methods.