Automatic modifications of high level VHDL descriptions for fault detection or tolerance

Author

Leveugle, R.

Author_Institution

TIMA Lab., Grenoble, France

fYear

2002

fDate

2002

Firstpage

837

Lastpage

841

Abstract

The need for integrated mechanisms providing on-line error detection or fault tolerance is becoming a major concern due to the increasing sensitivity of the circuits to their environment. This paper reports on a tool automating the implementation of such mechanisms by modifying high-level VHDL descriptions. The modifications are compatible with industrial design flows based on commercial synthesis and simulation tools. The results demonstrate the feasibility and the efficiency of the approach.

Keywords

digital integrated circuits; error detection; fault tolerance; hardware description languages; high level synthesis; integrated circuit design; automated modification tool; automatic description modification; circuit environmental sensitivity; commercial synthesis tools; high level VHDL descriptions; industrial design flow compatibility; integrated fault tolerance mechanisms; on-line error detection; simulation tools; Aerospace electronics; CMOS technology; Circuit faults; Circuit simulation; Circuit synthesis; Electrical fault detection; Fault detection; Fault tolerance; Integrated circuit synthesis; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998396

Filename

998396