DocumentCode :
2456938
Title :
Accurate area and delay estimators for FPGAs
Author :
Nayak, Anshuman ; Haldar, Malay ; Choudhary, Alok ; Banerjee, Prith
fYear :
2002
fDate :
2002
Firstpage :
862
Lastpage :
869
Abstract :
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic design space exploration to synthesize hardware for a field programmable gate array (FPGA) which meets the user area and frequency specifications. We present an area estimator which is used to estimate the maximum number of configurable logic blocks (CLBs) consumed by the hardware synthesized for the Xilinx XC4010 from the input MATLAB algorithm. We also present a delay estimator which finds out the delay in the logic elements in the critical path and the delay in the interconnects. The total number of CLBs predicted by us is within 16% of the actual CLB consumption and the synthesized frequency estimated by us is within an error of 13% of the actual frequency after synthesis through Synplify logic synthesis tools and after placement and routing through the XACT tools from Xilinx. Since the estimators proposed by us are fast and accurate enough, they can be used in a high level synthesis framework like ours to perform rapid design space exploration
Keywords :
circuit CAD; delay estimation; field programmable gate arrays; high level synthesis; integrated circuit interconnections; integrated circuit layout; network routing; software tools; CLB consumption; FPGAs; MATLAB; Synplify logic synthesis tools; Xilinx XACT tools; Xilinx XC4010; area estimators; automatic design space exploration; compiler; configurable logic blocks; critical path logic element delay; delay estimators; field programmable gate array; hardware synthesis; high level image processing applications; high level signal. processing applications; high level synthesis framework; input MATLAB algorithm; interconnect delay; placement; rapid design space exploration; routing; synthesized frequency estimation error; user area specifications; user frequency specifications; Delay estimation; Field programmable gate arrays; Frequency estimation; Frequency synthesizers; Hardware; Logic; MATLAB; Program processors; Signal processing; Space exploration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998400
Filename :
998400
Link To Document :
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