A new 65nm LP metastability measurment test circuit

Author

Beer, Sebastian ; Ginosar, Ran

fYear

2012

fDate

14-17 Nov. 2012

Firstpage

1

Lastpage

4

Abstract

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown. Measurements are compared to simulations for a fabricated 65nm bulk CMOS circuit build.

Keywords

CMOS integrated circuits; calibration; circuit stability; failure analysis; integrated circuit reliability; measurement systems; synchronisation; system-on-chip; CMOS circuit; LP CMOS process; LP metastability measurement test circuit; MTBF; calibrating system; calibration circuits; digital on-chip measurement system; mean time between failures; multiple-clock domain system-on-chip; size 65 nm; synchronizer metastability measurements; Delay; Delay lines; Integrated circuit modeling; Measurement uncertainty; Synchronization; Temperature measurement; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical & Electronics Engineers in Israel (IEEEI), 2012 IEEE 27th Convention of

Conference_Location

Eilat

Print_ISBN

978-1-4673-4682-5

Type

conf

DOI

10.1109/EEEI.2012.6377044

Filename

6377044