Arithematic for VLSI Signal Processing

This paper presents a brief summary of some key algorithms for the implementation of digital signal processing systems that are suitable for realization via VLSI circuits. Examples of design approaches that are suitable for the implementation of fast adders, multipliers, and dividers are considered at the algorithm and logic design levels. Different algorithms may be used to vary the speed of an arithmetic element by an order of magnitude or more while the complexity varies by less than 50%.