DocumentCode
2457684
Title
Improved technology mapping for PAL-based devices using a new approach to multi-output boolean functions
Author
Kania, Dariusz
Author_Institution
Inst. of Electron., Silesian Univ. of Technol., Poland
fYear
2002
fDate
2002
Firstpage
1087
Abstract
An effective technology mapping for PAL-based devices is presented in this paper. The aim of this method is to cover a multiple-output function by a minimal number of PAL-based logic blocks. The product terms included in a logic block can be shared by several functions. Experimental results are compared to the classical technology mapping method
Keywords
Boolean functions; directed graphs; logic design; minimisation of switching nets; programmable logic arrays; CPLDs; PAL-based devices; directed graph; minimal number; minimised functions; multi-output Boolean functions; technology mapping; Automatic testing; Boolean functions; Design automation; Europe; IEEE Computer Society Press; Joining processes; Kernel; Logic devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998444
Filename
998444
Link To Document