DocumentCode :
2457714
Title :
Iterative abstraction using SAT-based BMC with proof analysis
Author :
Gupta, Aarti ; Ganai, Malay ; Zijiang Yang ; Ashar, Pranav
Author_Institution :
NEC Lab. America, Princeton, NJ, USA
fYear :
2003
fDate :
9-13 Nov. 2003
Firstpage :
416
Lastpage :
423
Abstract :
Resolution-based proof analysis techniques have been proposed recently to identify a sufficient set of reasons for unsatisfiability derived by a CNF-based SAT solver. We have adapted these techniques to work with a hybrid SAT solver. We use the proof analysis technique with SAT-based BMC, in order to, generate useful abstract models. Our abstraction procedure is used iteratively in a top-down framework, starting from the concrete design, where we apply BMC on increasingly more abstract models. We apply various SAT-based and BDD-based verification methods on these abstract models, in order to obtain proofs of correctness, or to perform deeper searches for counterexamples. We demonstrate the effectiveness of our prototype implementation on several large industry designs.
Keywords :
abstracting; binary decision diagrams; computability; formal verification; BDD based verification methods; CNF based SAT solver; SAT based BMC; SAT based verification methods; binary decision diagrams; bounded model checking; conjunctive normal form; iterative abstraction; resolution based proof analysis; satisfiability based BMC; Boolean functions; Circuits; Computer bugs; Data structures; Design methodology; Explosions; Laboratories; National electric code; Permission; Prototypes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
Type :
conf
DOI :
10.1109/ICCAD.2003.1257811
Filename :
1257811
Link To Document :
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