Title :
High-level modeling and design of asynchronous arbiters for on-chip communication systems
Author :
Rigaud, J.-B. ; Quartana, J. ; Fesquet, Laurent ; Renaudin, M.
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
Summary form only given. This work presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied from the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and dynamic priority arbiters
Keywords :
CMOS logic circuits; VLSI; asynchronous circuits; circuit CAD; high level synthesis; integrated circuit design; low-power electronics; CMOS technology; GALA SoCs; GALS SoCs; SoC communication systems; asynchronous arbiters; automated synthesis process; clockless arbiters; complex arbitration modules; delay-insensitive arbiters; delay-insensitive implementations; dynamic priority arbiters; high-level behavioral specifications; high-level modeling; low-power arbiters; on-chip communication systems; CMOS process; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Cogeneration; Delay; Libraries; Synchronization; System-on-a-chip;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998447
