Mismatch characterization of high-speed NoC links using asynchronous sub-sampling

This paper presents asynchronous sub-sampling techniques to measure delay mismatch of clock and data lanes in high-speed serial network-on-chip (NoC) links. The techniques allow the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs with multiple NoC links. It enables compensation of delay variations to realize high-speed NoC links with sufficient yield. The proposed techniques are demonstrated at NoC links as part of an MPSoC in 65nm CMOS technology, where the calibration leads to significant reduction of bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4mm on-chip interconnect.