Design methodology to distribute on-chip power in next generation integrated circuits

The performance of an integrated circuit depends strongly upon the power delivery network. With the introduction of ultra-small on-chip voltage regulators, novel design methodologies are needed to determine the location of these on-chip power supplies and decoupling capacitors. In this paper, the optimal location of the power supplies and decoupling capacitors is determined for different size and number of components. Optimization algorithms widely used for facility location problems are applied in the proposed methodology. The effect of the size, number, and location of the power supplies and decoupling capacitors on the power noise is also discussed.