Title :
Transforming arbitrary structures into topologically equivalent slicing structures
Author :
Peyran, Olivier ; Zhuang, Wenjun
Author_Institution :
Inst. of High Performance Comput., Singapore, Singapore
Abstract :
Floorplanning is an important step of IC design. Traditionally, floorplan representation has been segregated between slicing and non-slicing structures. We present a heuristic that translates any arbitrary structure into a slicing one, topologically equivalent to the initial one after a 1-D compaction
Keywords :
VLSI; circuit layout CAD; circuit optimisation; equivalent circuits; integrated circuit layout; network topology; 1D compaction; IC design; arbitrary structures; circuit optimisation; floorplan representation; floorplanning; heuristic; topologically equivalent slicing structures; very deep sub micron technologies; Automatic testing; Circuit optimization; Compaction; Design automation; Europe; Extremities; High performance computing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998455
