Estimation of power consumption in encoded data buses

Author

Ortiz, Alberto García ; Kabulepa, Lukusa D. ; Glesner, Manfred

Author_Institution

Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany

fYear

2002

fDate

2002

Firstpage

1103

Abstract

Because of the increasing importance of cross coupled capacitances in deep submicron technologies, it is of great interest to extend the existing high-level power estimation techniques by considering the spatial correlation between adjacent lines. This work addresses the modeling and estimation of power dissipation in on-chip buses based on the statistical properties of data sequences. Using the derived models, a power estimation technique is proposed and evaluated for various coding schemes. For different DSP applications, our results depict less than 5% discrepancy with precise bit level estimations

Keywords

VLSI; capacitance; digital signal processing chips; high level synthesis; integrated circuit design; low-power electronics; DSP applications; bit level estimations; cross coupled capacitances; data sequences; deep submicron technologies; encoded data buses; high-level power estimation techniques; on-chip buses; power consumption; spatial correlation; statistical properties; Analytical models; Capacitance; Data buses; Design automation; Digital signal processing; Electronic switching systems; Energy consumption; Microelectronics; Power system modeling; Statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998459

Filename

998459