VLSI Design and Analysis of Multipliers for Low Power

Low power multipliers with high clock frequencies play an important role in today´s digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. The layouts of the sub-blocks are drawn using Cadence Virtuoso to form the multipliers macros. DRC and LVS checks are performed using HerculesI and fed to RC-XT for parasitic extraction and to carry out post layout simulation and the power analysis using Astro rail. Delay and power dissipation of Wallace Tree multiplier is least whereas Array multiplier is a best for reduced area applications but not speed. In this work, the area of 5times5 Array multiplier is 67.73 times 7 mum² is the least compared to others. Each multiplier has to be selected depending on performance measures and nature of applications.