Title :
A complete phase-locked loop power consumption model
Author :
Duarte, David ; Vijaykrishnan, Narayanan ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Summary form only given. A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process
Keywords :
continuous time systems; modelling; phase locked loops; PLL dynamic behavior; PLL power consumption model; acquisition states; lock states; phase-locked loop; power consumption estimation; second-order continuous time system; Capacitance; Charge pumps; Energy consumption; Equations; Phase frequency detector; Phase locked loops; Resistors; Virtual reality; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998464
