DocumentCode
2458085
Title
Development of a high-speed image processor
Author
Nohsoh, Kazunori ; Akutagawa, Kiyoshi
Author_Institution
Nissan Motor Co. Ltd., Yokosuka, Japan
fYear
1988
fDate
1988
Firstpage
13
Lastpage
18
Abstract
The authors describe the NIP-III image processor, which can execute a wide variety of general image processing operations for automobile industry manufacturing applications. Sixteen processing units having the same architecture are connected in rows. Individual users can input desired instructions to each unit and also freely change the bus lines linking the units. The processing units are implemented by gate-array large-scale integrated circuits and can perform the arithmetic and logic functions needed for image processing. A high processing speed has been achieved without increasing the size of the circuits. The authors present the hardware architecture of the NIP-III and describe its processing capabilities.
Keywords
automobile industry; computer vision; computerised picture processing; digital signal processing chips; large scale integration; logic arrays; NIP-III image processor; automobile industry; bus lines; computerised image processing; gate-array large-scale integrated circuits; hardware architecture; logic functions; Arithmetic; Automobile manufacture; Circuits; Hardware; Image processing; Joining processes; Large scale integration; Logic functions; Manufacturing industries; Manufacturing processes;
fLanguage
English
Publisher
ieee
Conference_Titel
Automotive Applications of Electronics, 1988., IEEE Workshop on
Conference_Location
Dearborn, MI, USA
Type
conf
DOI
10.1109/AAE.1988.47588
Filename
47588
Link To Document