The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories

We have investigated the area and latency tradeoffs with respect to error correcting capability of fast bit-parallel binary BCH ECC decoders. In particular, we show that for a primitive BCH code of length n over GF(2^m) with a Hamming distance of at least 2t+1 the area and latency scale approximately as nm²t and mt, respectively. The results presented in this paper might be very useful, e.g., for assessing the performance overheads due to the ECC decoders in the future random access nanoelectronic memories, which are expected to have a significantly larger number of defects as compared to that of today´s CMOS memories.