Title :
Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation
Author :
Gunnam, Kiran K. ; Choi, Gwan S. ; Wang, Weihuang ; Kim, Euncheol ; Yeary, Mark B.
Author_Institution :
Dept. of ECE, Texas A&M Univ., College Station, TX
fDate :
Oct. 29 2006-Nov. 1 2006
Abstract :
The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi- cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.
Keywords :
cyclic codes; decoding; parity check codes; ASIC implementation; FPGA; check node reliability message; decoder complexity; low-density parity-check codes; on-the-fly computation; quasi cyclic LDPC codes; scheduling; Computer architecture; Decoding; Dynamic scheduling; Field programmable gate arrays; Message passing; Out of order; Parity check codes; Processor scheduling; Throughput; Turbo codes; Block LDPC; IEEE 802.11n; IEEE 802.16e; Wi-fi; WiMax; array LDPC; block-serial processing; decoder architecture; irregular LDPC; layered decoding; low-density parity-check (LDPC) codes; offset min-sum; on-the-fly computation; quasicyclic LDPC; turbo decoding message passing; vector processing;
Conference_Titel :
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0784-2
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2006.354944