Optimal design of a Half-Wave Cockroft-Walton Voltage Multiplier with minimum total capacitance

The half-wave Cockroft-Walton voltage multiplier (H-W C-W VM) is one of the most common AC-DC step-up topologies, known for its large voltage gain and its high efficiency. However, over the worldwide bibliography, the most of H-W C-W VM designers persist in using equal capacitances in every stage without considering an optimal design. The aim of this paper is to introduce a new designing method of H-W C-W VM that lays both on the choice of the adequate capacitance values to minimize the output voltage drop and ripple (so the voltage gain is maximized) as well as the calculation of the optimal number of stages that is necessary to produce the desired output voltage with the minimum total capacitance. The theoretical analysis is validated by PSPICE simulations and experimental results, accomplished on laboratory prototypes.