Post optimization of a clock tree for power supply noise reduction

The voltage drop incurred in the power supply in today´s VLSI chips to is a major concern known as power-supply noise. In sub one-volt supply voltage, noise of very few hundreds millivolts causes circuit malfunction. The reason for power supply noise is the fast and simultaneous transistor switching. While the logic signal switching is spread across the entire clock cycle, the switching of the clock tree and the sequential circuits are occurring simultaneously, causing high local current peaks. The clock related transistor switching is the primary contributor to power supply noise. This paper proposes to spread the switching of clock tree drivers in an attempt to reduce the peak-current, while maintaining the clock signal quality and low skew at the far end tree´s leaves where the sequential circuits are connected. A methodology of cell switching characterization was developed for fast computation of peak-current and other signals parameters. This computation is embedded in a branch and bound tree traversal. We propose a novel optimization algorithm based on clock tree delay-invariant branch transformation, replacing low-threshold by high-threshold and smaller size drivers. The algorithm was implemented in 40 nanometers design. We achieved a reduction of 50% of clock-tree peak-current.