A review: Hardware Implementation of AES using minimal resources on FPGA

Data protection in mobile as well as in computer networks is increasing day by day forcing developer to design the cryptographic algorithms. Also sending data securely over a transmission link is important in many applications. To solve this security issue the U.S. government adopted an algorithm Advanced Encryption Standard (AES) and is now used worldwide. As there is possibility that this algorithm may get hacked, hence this Paper presents the hardware for AES algorithm which can be implemented on Xilinx FPGA. The approach used to implement the AES algorithm is the use of Look Up Tables (LUTs). This approach will give the throughput be-tween 3Gbps to 4Gbps with minimum utilization of resources on FPGA. Results can be verified using appropriate CAD tools.