A review: Hardware Implementation of AES using minimal resources on FPGA

Author

Dhede, Onkar S. ; Shah, S.K.

Author_Institution

Dept. of Electron. & Telecommun. Eng., STES´s Smt. Kashibai Navale Coll. of Eng., Pune, India

fYear

2015

fDate

8-10 Jan. 2015

Firstpage

1

Lastpage

3

Abstract

Data protection in mobile as well as in computer networks is increasing day by day forcing developer to design the cryptographic algorithms. Also sending data securely over a transmission link is important in many applications. To solve this security issue the U.S. government adopted an algorithm Advanced Encryption Standard (AES) and is now used worldwide. As there is possibility that this algorithm may get hacked, hence this Paper presents the hardware for AES algorithm which can be implemented on Xilinx FPGA. The approach used to implement the AES algorithm is the use of Look Up Tables (LUTs). This approach will give the throughput be-tween 3Gbps to 4Gbps with minimum utilization of resources on FPGA. Results can be verified using appropriate CAD tools.

Keywords

circuit CAD; cryptography; field programmable gate arrays; resource allocation; table lookup; AES; CAD tools; LUT; US government; Xilinx FPGA; advanced encryption standard; computer networks; cryptographic algorithms; data protection; hardware implementation; look up tables; minimal FPGA resources; minimum resources utilization; security issue; transmission link; Algorithm design and analysis; Encryption; Field programmable gate arrays; Hardware; Software; Software algorithms; AES (Advance Encryption Standard); Backend design; Field Programable Gate Array (FPGA); Frontend design; LUT´s; Troughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Pervasive Computing (ICPC), 2015 International Conference on

Conference_Location

Pune

Type

conf

DOI

10.1109/PERVASIVE.2015.7087187

Filename

7087187