Title :
Comparison of Montgomery and Barrett modular multipliers on FPGAs
Author :
Kong, Yinan ; Phillips, Braden
Author_Institution :
Centre for High Performance Integrated Technol. & Syst. (CHiPTec) Sch. of Electr. & Electron. Eng., Univ. of Adelaide, Adelaide, SA
fDate :
Oct. 29 2006-Nov. 1 2006
Abstract :
A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.
Keywords :
digital arithmetic; field programmable gate arrays; multiplying circuits; pipeline processing; Barrett modular multipliers; FPGA; Montgomery modular multipliers; quotient pipelining; trivial quotient digit selection; Australia; Computer architecture; Cryptography; Delay; Digital arithmetic; Field programmable gate arrays; Image processing; Logic; Pipeline processing; Timing; FPGA; computer arithmetic; modular multiplication;
Conference_Titel :
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0784-2
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2006.355048
