A boundary scan architecture using multiple-valued logic

A boundary scan scheme is introduced that uses multiple-valued logic signaling to reduce the number of chip pins and on-chip control signal lines, which leads to a decrease in the chip area overhead as well as interconnection complexity. The various modes of operation in the proposed scheme are defined by the quaternary control line CS (control signal). Also encoded on CS is the clock signal used to synchronize the data movement in the boundary scan shift register path. The proposed scheme does not allow the application of the clock pulses through BSI during the apply test mode of operation. However, application of clock pulses during this mode has no apparent use since data cannot be shifted out