A CMOS binary adder using a quaternary ganged-logic internal node

The design of a novel complementary metal-oxide semiconductor (CMOS) binary full-adder structure that incorporates four-valued signaling internally is described. A biased CMOS pseudolinear adder provides a quaternary signal representing the number of ones in the three binary inputs. Three area-ratioed CMOS inverters interpret this to provide three binary signals, which, combined in conventional static CMOS logic, generate the sum and carry outputs. The resulting ganged-logic adder is competitive in situations where higher static power dissipation and reduced internal noise margins can be tolerated in exchange for much lower input capacitance and faster carry propagation