Optimized design of a high frequency digital controller for DVS-enabled adaptive DC-DC converter

Proliferation of mobile electronic equipment has led to the study and development of several management techniques for managing the battery power source. Dynamic voltage scaling (DVS) is an accepted solution. An optimized hardware of an analog to digital converter (ADC) is presented here. A novel formulation of digital error value based on reference clock frequency and converter output voltage is introduced in this paper. Resolution limitation of hybrid digital pulse width modulator (DPWM) with increased switching frequency is addressed by utilizing an edge-triggered hybrid DPWM design that achieves both linear and high resolution. Support for process, voltage, temperature (PVT) variations is incorporated in the integrated design framework. A synchronous buck converter of 1 MHz switching frequency and a delay line with discrete components have been fabricated for realizing and verifying the complete closed-loop prototype. Experimental results are presented, which demonstrate the fast dynamic response achieved with a reference clock frequency in the 6-16 MHz range, corresponding to a regulated output voltage range of 1.6 - 3.2 Volts. The complete design of digital controller ICs has been implemented in 0.5 mum CMOS technology using Cadence and Synopsys tools. The active on-chip area of the proposed delay line ADC, digital compensator and edge-triggered hybrid DPWM are 0.08 mm²,0.28 mm² and 0.07 mm² respectively.