Design and construction of a bus bar for spike reduction in an industrial inverter

This paper presents a practical method to improve inverter dc bus bar configuration in order to minimize voltage spike. Many parameters are affected by voltage spike such as dc capacitor bank size, EMI noise reduction, elimination of snubber and finally voltage stability and IGBT safety. This approach proposes planar bus bars with minimum space and maximum overlapping between them in order to reduce bus bars stray inductance. Simulation of bus bar structures gives basic idea about which structure provides less stray inductance. To confirm advantages of these method experimental results from an 80-kVA UPS are presented which shows 63% voltage spike reduction.