An efficient hardware implementation of high quality AWGN generator using Box-Muller method

Box Muller (BM) algorithm is extensively used for generation of high quality Gaussian Random Numbers (GRNs) in hardware. Most efficient published implementation of BM method utilizes transformation of 32-bit data path to 16 bits and use of first degree piece-wise polynomial approximation to compute logarithmic and square root functions. In this work, we have performed extensive error analysis to show that coefficient memory for polynomial approximation can be reduced by more than 35 percent without compromising on quality of generated Gaussian samples. This also reduces complexity of corresponding address generator, which requires most hardware resources. We have also used more efficient and statistically accurate skip-ahead Linear Feedback Shift Registers to generate uniformly distributed numbers for the BM algorithm. Complete hardware implementation utilizes only 407 slices, 03 DSP blocks and 1.5 memory blocks on Xilinx Virtex-4 XC4VLX15 operating at 230 MHz while providing a tail accuracy of 6.6σ. This is better in terms of accuracy and hardware utilization than any of the previously reported architecture.