Fault tolerant and testable designs of reversible sequential building blocks

With increasing high speed computation demand the power consumption, heat dissipation and chip size issues are posing challenges for logic design with conventional technologies. Recovery of bit loss and bit errors is other issues that require reversibility and fault tolerance in computation. The reversible computing is emerging as an alternative to conventional technologies to overcome above problems. Bit loss issue can be solved through unique input output mapping which require reversibility and bit error issue require capability of fault tolerance in design. In order to incorporate reversibility a number of combinational reversible logic based circuits have been developed. However, very few sequential reversible circuits have been reported in the literature. To make the circuit fault tolerant, a number of fault model and test approaches have been proposed for reversible logic. In this paper, we have attempted to incorporate fault tolerance in sequential reversible building blocks such as positive level D flip-flop, negative level D flip-flop, T flip-flop, JK flipflop, R-S flip-flop, Master-Slave D flip-flop and double edge triggered (DET) D flip-flop by making them parity preserving. The importance of this proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault and single bit fault. In our opinion our design of reversible building blocks is superior to existing designs in term of quantum cost, hardware complexity, constant input, garbage output, number of gates and design of online testable D flip-flop have been proposed for the first time. We hope our work can be extended for building complex reversible sequential circuits.