DocumentCode
2465659
Title
Two-stage Miller-compensated amplifier with embedded negative current buffer
Author
Ho, Marco ; Leung, Ka Nang
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin
fYear
2008
fDate
8-10 Dec. 2008
Firstpage
1
Lastpage
4
Abstract
A two-stage simple Miller-compensated (SMC) amplifier with embedded negative current buffer design is presented in this paper. The compensation technique based on current buffer allows elimination of the right half-plane zero in SMC system, offers significant improvement in bandwidth and considerably lowers the compensation capacitance requirement. Simulation results show that the unity-gain frequency is extended by 22.6 times by the proposed design, while the power consumption is only increased by 28.3%. The required compensation capacitance is also decreased by 28 times.
Keywords
amplifiers; capacitance; power consumption; compensation capacitance; negative current buffer; power consumption; two-stage Miller-compensated amplifier; unity-gain frequency; Bandwidth; Capacitors; Cause effect analysis; Circuits; Energy consumption; Frequency; Parasitic capacitance; Sliding mode control; Stability; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-2539-6
Electronic_ISBN
978-1-4244-2540-2
Type
conf
DOI
10.1109/EDSSC.2008.4760638
Filename
4760638
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