Title :
Optimal technology mapping for single output cells
Author :
Hinsberger, Uwe ; Kolla, Reiner
Author_Institution :
Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany
Abstract :
This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mapping based methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for duplication of logic and for AT-tradeoffs are developed and applied to LUT-FPGAs
Keywords :
Boolean functions; circuit optimisation; delays; field programmable gate arrays; logic CAD; table lookup; AT-tradeoffs; Boolean functions; DAG-mapping; LUT-FPGAs; cost functions; duplication-free mapping; logic duplication; lookup table; minimum delay mapping; optimal technology mapping; single output cells; Adders; Boolean functions; Circuits; Contracts; Cost function; Delay; Hardware; Logic; Multiplexing; Virtual colonoscopy;
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
Print_ISBN :
0-8186-7035-5
DOI :
10.1109/GLSV.1995.516017
