Low power wireless receiver in CMOS mixed-signal for bio-telemetry implantable system

A novel mixed-signal interlace is presented for implantable interlace receiver consists of an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an ASK demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated, low-power circuit. We also developed the processing circuit with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10 MHz range, the data rates up to IM bits are supported, suitable for complex implantable microsystem such as the brain neural mutual interface and so on. Low-power and high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-mum CMOS technology. The power dissipation of the mixed-signal micros stem is verified to be less than 2.75 mW @ 1.8 V.