Cascaded classification for hardware face detection

This paper presents a face detection hardware architecture which is based on a newly proposed algorithm using cascaded classifiers with vector angle similarity measurement between the investigated image and the face/non-face centroids. The proposed system is composed of three major modules: Best fit plane removal unit, Histogram equalization unit, and cascaded classification unit. Comprehensive optimization at both the algorithmic and hardware levels has enabled performance improvement and area reduction. The vector angle similarity measure-based algorithm is employed to achieve acceptable classification accuracy and high-speed. The cascaded classification architecture is designed in a parallel mode to achieve low latency and low iteration time. The overall system was designed in VHDL and synthesized and implemented using Xilinx FPGA vertex4 family board. Experimental results on real-time captured face images prove the system reliability and achievement of real-time classification performance which is comparable to a software implementation while running at a frame rate of 63 frames per second at an image resolution of 64times64 pixels. The proposed architecture is scalable and can be extended to higher resolution.