DocumentCode :
2466946
Title :
Test Generation Based on SVM for Analog System with a Multi-training Sets Method
Author :
Long, Ting ; Wang, Houjun ; Long, Bing
Author_Institution :
Sch. of Autom. Eng., Electron. Sci. & Technol. Univ., Chengdu, China
fYear :
2010
fDate :
17-19 Dec. 2010
Firstpage :
1186
Lastpage :
1189
Abstract :
This paper proposes a novel analog test generation based on the SVM (support vector machine) with a multitraining sets method. The test generation method in this paper generates test signals directly from the sample space of the output responses of the analog DUT. The training sets are randomly generated in the test generation, so we use a multitraining sets method to avoid the influence of choosing different training sets. This method can avoid achieving the worst misclassification rate. The experiment confirms that it can enhance the efficiency of the test generation.
Keywords :
analogue circuits; circuit analysis computing; circuit testing; support vector machines; SVM; analog DUT; analog system; multitraining sets method; support vector machine; test generation method; Analog circuits; Circuit faults; Classification algorithms; Support vector machines; Testing; Training; Vectors; SVM (support vector machine); analog systems; misclassification rate; multi-training sets; test generation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational and Information Sciences (ICCIS), 2010 International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-8814-8
Electronic_ISBN :
978-0-7695-4270-6
Type :
conf
DOI :
10.1109/ICCIS.2010.293
Filename :
5709493
Link To Document :
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