A dual band CMOS two-stage variable gain low noise amplifier

A low power CMOS fully-integrated on-chip inductor-less low noise amplifier (LNA) designed for short range devices (SRDs) in 0.25-mum CMOS process is presented. It is working at 315 MHz and 433 MHz. Common gate input topology is adopted to realize wideband impedance matching without tuning. Cross coupled common-gate input technique is adopted to improve the noise performance of conventional common-gate LNA. Two-stage variable gain architecture is used to optimize the gain, noise and linearity simultaneously. The simulated S₁₁ is below -17 dB across the entire band and the minimum noise figure is 2.55 dB when the gain is set to the highest. The LNA provides a gain control range of 36 dB and the simulated IIP3 is -2.7 dBm. The power consumption is 5.5 mW without the output buffer at a 2.5 V supply voltage. The core circuit area is 0.33 mm times 0.18 mm.